Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 684

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The shift register input pins (

default to the external shift register pins (

The processor contains registers that are used to control the shift register.

• Control Register (SHREGCTL). Used to clear/reset the shift reg-

ister in software, select the data source for the

the 18 bits of the register, and to enable parallel data output. Com-

plete bit description can be found at TBD.

• Clock Routing Register (SRU_CLK_SHREG). Configures the

clock source.

(SRU_CLK_SHREG)" on page A-145.

• Data Routing Register (SRU_DAT_SHREG). Configures the data

For more information, see "Data Routing Register

(SRU_DAT_SHREG)" on page A-147.

The shift register requires two clock inputs:

out of many sources such as the SPORTs, PCGA/B, DAI pin buffers 8–1,

or dedicated

ing edge of the

to the latch on rising edge of the

together, the shift register is always one clock pulse ahead of the latch.

www.BDTIC.com/ADI

For more information, see "Clock Routing Register

for the latch. The source of these clocks is selectable

input pins. The data is shifted on the ris-

and the data from the shift register is transferred

ADSP-214xx SHARC Processor Hardware Reference

for the serial shift

. If both clocks are connected

) are routed by

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