Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 574

SRU Programming
Table 13-2. S/PDIF Transmitter Pin Descriptions (Cont'd)
Internal Node
DIT_O
DIT_BLKSTART_O Output
1 Timing for the S/PDIF format consists of time slots, unit intervals, subframes, and frames. For a
complete explanation of S/PDIF timing, see one of the digital audio interface standards listed in
the "Features" section of this chapter.
Table 13-3 provides descriptions of the pins used for the S/PDIF receiver.
Table 13-3. S/PDIF Receiver Pin Descriptions
Internal Node
SPDIF_EXTPLLCLK_I
DIR_I
DIR_CLK_O
DIR_TDMCLK_O
DIR_FS_O
DIR_DAT_O
DIR_LRCLK_FB_O
DIR_LRCLK_REF_O
SRU Programming
The SRU (signal routing unit) is used to connect the S/PDIF transmitter
biphase data out to the output pins or to the S/PDIF receiver. The serial
13-4
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I/O Description
Output Transmit Biphase Mark Encoded Data Stream.
Transmit Block Start. Indicates the last frame of the
current block. This is high for the entire duration of
the last frame. This can also be connected to the
DAI interrupts 31–22 using SRU_MISCx registers.
I/O Description
Input PLL clock input (512
external PLL.
Input Biphase mark encoded data receiver input stream.
Output Extracted receiver sample clock output.
Output Receiver TDM clock out. This clock is 256
DIR_FS_O.
Output Extracted receiver frame sync out.
Output Extracted audio data output.
Output Receiver frame sync feed back output. Input for
external PLL.
Output Receiver frame sync reference clock output. Input
for external PLL.
ADSP-214xx SHARC Processor Hardware Reference
×
FS). Input clock from
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