Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 878

ADSP-2147x, ADSP-2148x External Port Registers
SDADDRMODE
Address Map Mode
PGSZ 128
Page size is 128 bits
SDRAW (29–27)
Row Address Width
STDRCD (26–24)
SDRAM tRCD Specification
SDBUF
Pipeline Option with External Register Buffer
SDSRF
SDRAM Self Refresh Enable
SDPSS
SDRAM Power-up Sequence Start
SDCAW (13–12)
SDRAM Bank Column Address Width
SDPM
SDRAM Power-Up Mode
Figure A-23. SDCTL Register
A-52
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31 30 29 28 27 26 25 24
15 14 13 12 11 10 9 8
ADSP-214xx SHARC Processor Hardware Reference
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1 0
SDCL (2–0)
CAS Latency
DSDCTL
Disable SDCLK and Control
Signals
DSDCTL1
Disable SDCLK1 and Control
Signals
SDTRAS (7–4)
SDRAM tRAS Specification
SDTRP (10–8)
SDRAM tRP Specification
X16DE
SDRAM External Data Path Width
SDTWR (18–17)
SDRAM tWR Specification
SDORF
Optional Refresh
FAR
Force Auto Refresh
FPC
Force Precharge
Force LMR
Force Auto Load Mode
Register