Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 640

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Interrupts
Full Duplex Operation
The SPI interface allows full-duplex operation running the DMA channel
to the transmit/receive path and core access to the alternate trans-
mit/receive path. For full-duplex operation, set
generates the interrupts for DMA only.
Reads from the
DMA. Note the
DMA FIFO is not available in the receive path. The receive interface can-
not generate an interrupt, but the
Writes to the
TXSPIx
are permitted. Note the
but the DMA FIFO is not available in the transmit path. The transmit
interface cannot generate an interrupt, but the
polled.
Interrupts
The following section describes SPI operations using both the core and
direct memory access (DMA).
interrupts.
Interrupt Sources
The SPI ports can generate interrupts in five different situations. During
core-driven transfers, an SPI interrupt is triggered:
1. When the
from the core.
2. When the
core.
15-24
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buffer are allowed at any time during transmit
RXSPIx
bit is cleared when the
TXS
RXS
buffer during an active SPI receive DMA operation
bit is cleared when the
RXS
Table 15-7
buffer has the capacity to accept another word
TXSPI
buffer contains a valid word to be retrieved by the
RXSPI
ADSP-214xx SHARC Processor Hardware Reference
= 10 which
TIMOD
buffer is read but the
TXSPIx
status bits can be polled.
RXSPIx
status bits can be
TXS
provides an overview of SPI
buffer is read

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