Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 650

Programming Model
receive DMA the status bit is asserted when the DMA count becomes
zero. For transmit DMA the
• the DMA count becomes zero and
• the DMA FIFO becomes empty and
• the
SPITX
• transfer is complete (
Note that the
SPIFE
chained DMA.
Switching From Transmit to a New DMA
The following sequence details the steps for switching from transmit to
transmit/receive DMA.
With SPI disabled:
1. Poll the
can be disabled.
2. Clear the
clears the
3. Disable DMA by clearing the
4. Clear all errors by writing to the W1C-type bits in the
registers. This ensures that no interrupts occur due to errors from a
previous DMA operation.
5. Reconfigure the
6. Configure DMA by writing to the DMA parameter registers and
the
SPIDMACx
15-34
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SPIFE
buffer becomes empty (
bit goes high)
SPIF
bit can go high between two DMA blocks of a
bit in the
SPIFE SPISTAT
register to disable the SPI. Disabling the SPI also
SPICTLx
/ buffer and the buffer status.
RXSPIx TXSPIx
register and enable the SPI ports.
SPICTLx
registers using the
ADSP-214xx SHARC Processor Hardware Reference
goes high when:
bit high) and
TXS
register. If this bit is high the SPI
register.
SPIDMACx
bit (bit 0).
SPIDEN
SPISTATx