Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 153

Figure 3-5 and
processors.
SDCLK
COMMAND ACT
ROW
ADDR
A
BA[1:0]
DATA
Figure 3-5. Write Timing Diagram
SDCLK
COMMAND ACT
ROW
ADDR
A
BA[1:0]
DATA
Figure 3-6. Read Timing Diagram
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Figure 3-6 show the SDRAM write and read timing of the
NOP WR WR
COL COL
A A
D D
t RCD
NOP RD RD
COL COL
A A
t RCD
t RAS
WR WR NOP
COL COL
A A
D D
t WR
t RAS
t RC
NOP NOP NOP
D
CL
t RC
External Port
PRE
NOP ACT
ROW
t RP
PRE
NOP
D
t RP
3-23
A
ACT
ROW
A