I 2 S Mode; Master Serial Clock And Frame Sync Rates; Timing Control Bits - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Operation Modes
SPORTx_CLK
SPORTx_FS/WS
LEFT-JUSTIFIED SAMPLE
PAIR MODE
SPORTx_DA/DB DATA
SAMPLE n-1
Figure 10-6. Word Select Timing in Left-Justified Mode
2
I S Mode
The following sections provide information on using I

Master Serial Clock and Frame Sync Rates

The serial clock rate (
bit field in the
DIVx
can be set using the
bit setting.
The transmitter sends the MSB of the next word in the same clock cycle as
the word select (
continuously in I
ple, for 8-bit data words set

Timing Control Bits

Several bits in the
operation:
• Master Mode Clock and Frame Sync (
• Sampling Edges Frame Sync/Data (
10-30
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LSB n-1 MSB n
LEFT CHANNEL
value) for internal clocks can be set using a
CLKDIV
register and the frame sync rate for internal frame sync
bit field in the
FSDIV
) signal changes. To transmit or receive words
SPORTx_FS
2
S mode, load the
= 7.
FSDIV
register enable and configure I
SPCTLx
ADSP-214xx SHARC Processor Hardware Reference
LSB n
SAMPLE n
2
register based on the
DIVx
register with
FSDIV
)
MSTR
)
CKRE
MSB n+1
SAMPLE n+1
S mode.
MSTR
–1. For exam-
SLEN
2
S mode