Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 841

Power Management Control Register 1
(PMCTL1)
This register contains the bits for shutting down the clocks to various
peripherals and selecting one of the three FIR/IIR/FFT accelerators. The
core can write to bits 19–0 of this register.

Writes to this register have an effect latency of two
31 30
MLBOFF
MLB Clock Shutdown
ACCSEL (18–17)
Accelerator Select
15
RTCOFF
RTC Clock Shutdown
TMROFF
Timer Clock Shutdown
SPIOFF
SPI Clock Shutdown
SP67OFF
SP6/7 Clock Shutdown
SP45OFF
SP4/5 Clock Shutdown
SP23OFF
SP2/3 Clock Shutdown
SP01OFF
SP0/1 Clock Shutdown
Figure A-5. PMCTL1 Register
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
Registers Reference
21 20 19 18 17 16
ACCOFF
Accelerator Clocks
Shutdown
6 5 4 3 2 1 0
UART0POFF
UART Clock Shutdown
TWIOFF
TWI Clock Shutdown
PWMOFF
PWM Clock Shutdown
DTCPOFF
DTCP Clock Shutdown
DAIOFF
Shutdown Clock to SRC,
SPDIF, SRU, PCG, DAI, IDP,
PDAP
EPOFF
EP Clock Shutdown
cycles.
PCLK
A-15