Iir Accelerator Tcb - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

IIR Accelerator TCB

The IIR accelerator supports circular buffer chained DMA.
shows the required TCBs for chained DMA.

In the IIR accelerator DMA, two different TCB loading sequences
are available: one TCB loads five parameters for the coefficients
(
IIRCTL2
parameters for the data (
,
OMIIR OCIIR
Table 2-19. IIR TCBs
Address
CP[18:0]
CP[18:0] + 0x1
CP[18:0] + 0x2
CP[18:0] + 0x3
CP[18:0] + 0x4
CP[18:0] + 0x5
CP[18:0] + 0x6
CP[18:0] + 0x7
CP[18:0] + 0x8
CP[18:0] + 0x9
CP[18:0] + 0xA
CP[18:0] + 0xB
CP[18:0] + 0xC
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
, , ,
CIIIR CMIIR CCIIR
IIRCTL2
, and
OBIIR CPIIR
Register
CPIIR
CCIIR
CMIIR
CIIIR
OBIIR
OCIIR
OMIIR
OIIIR
IBIIR
ICIIR
IMIIR
IIIIR
IIRCTL2
and ). The second loads 10
CPIIR
, , ,
IIIR IMIIR ICIIR
).
I/O Processor
Table 2-19
, , ,
IBIIR OIIIR
2-17