Changing The Link Port Clock - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Changing the Link Port Clock

The following programming sequence may be used to change the
core-to-link port clock ratio only. Note that this procedure changes only
the PLL output divider. Therefore programs do not need to wait 4096
cycles (required only if the PLL multiplier or the
CLKIN
modified).
1. Disable the link ports. Note that the peripherals cannot be enabled
when changing clock ratio.
2. Select the PLL divider by setting the
register).
PMCTL
3. Select the link port clock divider (
the
LPCKRx
4. Enable the new divisors by setting the
register).
5. Wait 15
any valid instructions. The
on-the-fly. This means that when a clock ratio change is registered,
the current clock cycle may get truncated before the change and the
new clock cycle ratio start.
6. Enable link ports.
For more information on link port clocking and programming the PLL,
see "Phase-Locked Loop (PLL)" on page
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
bits (bits 21 and 22 in the
cycles. During this time, programs must not execute
CCLK
LPCLK
Link Ports—ADSP-2146x
INDIV
bits (bits 6–7 in the
PLLDx
to ratio) by setting
CCLK LPCLK
register).
PMCTL
bit (bit 9 in the
DIVEN
change does not happen
22-2.
bit is
PMCTL
4-23