Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 883

Controller Status Register 1 (SDSTAT1)
This register reports the SDRAM bank active/idle status. This register is
shown in Figure A-25
15
Bit Field (15–12)
External Bank 1
Status
Bit Field (11–8)
External Bank 3
Status
Figure A-25. SDSTAT1 Register
Table A-30. SDSTAT1 Register Bit Descriptions (RO)
Bit Field
7–0
15–8
ADSP-214xx SHARC Processor Hardware Reference
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and described in
14 13 12 11 10 9 8
Field Name Description
External Bank 0 External Bank 0 Active/Precharge State.
Status xxx1 = Internal bank 0 in open state
xxx0 = Internal bank 0 in precharge state
xx1x = Internal bank 1 in open state
xx0x = Internal bank 1 in precharge state
...
1xxx = Internal bank 7 in open state
0xxx = Internal bank 7 in precharge state
External Bank 1 External Bank 0 Active/Precharge State.
Status xxx1 = Internal bank 0 in open state
xxx0 = Internal bank 0 in precharge state
xx1x = Internal bank 1 in open state
xx0x = Internal bank 1 in precharge state
...
1xxx = Internal bank 7 in open state
0xxx = Internal bank 7 in precharge state
Registers Reference
Table A-30.
7 6 5 4 3 2 1 0
Bit Field (3–0)
External Bank 0
Status
Bit Field (7–4)
External Bank 2
Status
A-57