Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 623

Table 15-4. SPI BAUD Rate – PCLK = 200 MHz (Cont'd)
BAUDR Bit Setting
4
25
32,767
Choosing the Pin Enable for the SPI Clock
When using the SPI in master mode, and the
onto the DPI pin, then the
used for the clock must be connected to high.
However, depending on the SPI mode being used (based on the setting of
and
CPHASE CLKPL
be used.
Choosing the correct pin enable ensures that the very first edge on
(DPI pin) output is not incorrectly chosen as a sampling edge by
SPIx_CLK
the slave SPI. Table 15-5
SPI mode.
Table 15-5. Pin Enable Selection by Mode
Mode CLKPL
0 0
1 0
2 1
3 1
All other SPI signals
routed on the DPI pins, the
SPIx_FLG_PBEN_O
signals. The
DPI_PBENxx_I
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Serial Peripheral Interface Ports
Divider SPICLK
16 12.5
100 2.0 (master boot)
131068 1526 Hz
DPI_PBENxx_I
bits in the register),
SPICTL
shows the correct pin enable to use for a chosen
CPHASE Pin Enable
0 HIGH
1 HIGH
0 SPIx_CLK_PBEN_O
1 SPIx_CLK_PBEN_O
,
SPIx_MOSI SPIx_MISO
SPIx_MISO_PBEN_O
signals should be connected to corresponding
DPI_PBENxx_I
signal is routed
SPIxCLK
signal for that DPI pin being
SPIx_CLK_PBEN_O
and signals when
SPIx_FLGx
,
SPIx_MOSI_PBEN_O
signals should not be statically
signal may
, or
15-7