Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 758

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Programming Model

When enabled, slave mode supports both receive and transmit data trans-

fers. It is not possible to enable only one data transfer direction and not

acknowledge (NAK) the other. This is reflected in the following setup.

1. Program the

determining a match during the address phase of the transfer.

2. Program the

values to be transmitted in the event the slave is addressed as a

transmitter. This is an optional step. If no data is written and the

slave is addressed and a transmit is required, the

stretched and an interrupt is generated.

3. Program the

FIFO buffer interrupts should occur with each byte transmitted

(received) or with each 2 bytes transmitted (received).

4. Program the

desired interrupt sources. As an example, programming the value

0x000F results in an interrupt output to the processor when a valid

address match is detected, a valid slave transfer completes, a slave

transfer has an error, or a subsequent transfer has begun but the

previous transfer has not been serviced.

5. Program the

mode operation. As an example, programming the value 0x0005

enables slave mode operation, requires 7-bit addressing, and indi-

cates that data in the transmit FIFO buffer is intended for slave

mode transmission.

shows what the interaction between the TWI controller and

the processor might look like when the slave is addressed as a receiver.

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ADSP-214xx SHARC Processor Hardware Reference

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