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internally connected acknowledge signal, as controlled by refresh, or page
miss latency overhead.
A programmable refresh counter is provided which generates background
auto-refresh cycles at the required refresh rate based on the clock fre-
quency used. The refresh counter period is specified with the
the SDRAM refresh rate control register
(SDRRC)" on page
The internal 32-bit non-multiplexed address is multiplexed into:
• SDRAM column address
• SDRAM row address
• Internal SDRAM bank address
Based on the addressing mapping bit (
mapped into the column address, next bits are mapped into the row
address, and the final two bits are mapped into the internal bank address.
If
= 1 the lowest bits are mapped into the column address, next
ADDRMODE
bits are mapped into the internal bank address and the final bits are
mapped into the row address. This mapping is based on the
values programmed into the SDRAM control register.
SDRAW
The SDC uses no burst mode (BL = 1) for read and write operations. This
requires the SDC to post every read or write address on the bus as for
non-sequential reads or writes, but does not cause any performance
degradation.
For read commands, there is a latency from the start of the read command
to the availability of data from the SDRAM, equal to the CAS latency.
This latency is always present for any single read transfer. Subsequent
reads do not have latency.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
A-58).
ADDRMODE
External Port
("Refresh Rate Control Register
= 0) the lowest bits are
field in
RDIV
and
SDCAW
3-19
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