Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 524

Pin Descriptions
Table 11-3. PDAP Pin Descriptions (Cont'd)
Internal Nodes
PDAP_STRB_O
Table 11-4 provides descriptions of the pin multiplexing between DAI
and external port.
page 23-28.
Table 11-4. Pin Multiplexing between DAI and External Port
Signal
Serial Clock
Frame Sync
Data
Strobe Out
11-4
www.BDTIC.com/ADI
Type Description
O Parallel Data Acquisition Port Clock input. The PDAP packing
unit asserts the output strobe whenever there is 32-bit data available
for transfer to the IDP FIFO. The width of this pulse is equal to 2 x
PCLK cycles. This signal can be used to synchronize external
requests for new PDAP data. Note that input has multiplexed con-
trol.
For more information, see "Pin Multiplexing" on
DAI
IDP0_CLK_I
IDP0_FS_I
DAI_PB20–1
PDAP_STRB_O
ADSP-214xx SHARC Processor Hardware Reference
External Port
DATA[10]
DATA[11]
DATA[31–12]
DATA[8]