Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 712

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Programming Model
period value into the 32-bit
enabled. Once the watchdog is started, the period value cannot be altered.
To start the watchdog timer:
1. Unlock the WDT configuration registers by writing the unlock
"command" value to the
programming the
By Default, the resonator output is
2. Set the trip counter value for the watchdog timer by writing to the
WDTTRIP
3. Set the count value for the watchdog timer by writing the count
value into the watchdog period register (
dog timer is not yet enabled, the write to the
automatically pre-loads the
sufficient time must be provided for the write to the
ister to occur (2.5
4. Enable the watchdog timer in
5. Lock the WDT configuration registers by writing to the
register. The watchdog timer begins counting down, decrementing
the value in the
ware does not serve the watchdog in time,
decrementing until it reaches 0 and the system is reset.
The counter now reloads the
keeps decrementing. Additionally, the WDRO latch bit in the
register is set and can be interrogated by software. This
STATUS
occurs up to the number of times programmed in the
ister. When
6. To prevent the watchdog from expiring, software serves the watch-
dog by unlocking the WDT configuration space and performing
dummy writes to the
19-8
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WDTCNT
WDTUNLOCK
WDTCLKSEL
register.
cycles max.), before enabling WDT.
WDTCLK
register every
WDTCURCNT
expires, WDT holds the
WDTTRIP
WDTCURCNT
ADSP-214xx SHARC Processor Hardware Reference
register before the watchdog is
register. Select the
bit.
.
WDTCLK
WDTCNT
WDTCNT
register as well. Note that
WDTCURCNT
.
WDTCTL
WDT_CLKIN
WDTCURCNT
value from
WDTCURCNT
WDTRSTO
register address in time. The values
by
WDTCLK
). Since the watch-
registers
reg-
WDTCURCNT
WDTUNLOCK
cycle. If soft-
continues
and
WDTCNT
WDT-
reg-
WDTTRIP
asserted.

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