Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 411

Interrupt Source
One interrupt is shared by the system status and channel status interrupts.
Servicing Interrupts
System status interrupts interrupts are generated on events that allow sys-
tem software to monitor and control the status of the MediaLB Network.
These interrupts can be unmasked by clearing the corresponding bit in
register. The interrupt is cleared within the ISR before the RTI
MLB_SMCR
instruction by writing one to corresponding bit in the
Channel status interrupts are generated on events corresponding to a par-
ticular logical channel (0–31). These interrupts can be unmasked by
clearing the appropriate bits (16–23) in the
The channel interrupt status register (
tus of the individual logical channels. For example, if an interrupt is
pending in logical channel 0, the corresponding bit (bit 0) is set in the
register. These bits are set by hardware when a channel interrupt
MLB_CICR
is generated. The channel interrupt bits are sticky and can only be reset by
software. To clear a particular bit in the
clear all of the unmasked status bits in the corresponding
ters. Therefore, if bit 0 of the
bit 0 register clears
MLB_CSCR
the channel interrupt ISR before the RTI instruction to ensure that the
interrupt is not regenerated.
Debug Features
The following sections provide information to assist in MediaLB debug.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
MLB_CECRx
) reflects the interrupt sta-
MLB_CICR
MLB_CICR
register is set, writing 0xFFFF to
MLB_CICR
bit 0. This step must be included
MLB_CICR
Media Local Bus
register.
MLB_SSCR
register.
register, software must
regis-
MLB_CSCRn
8-15