Frequency Change In Precharge Power-Down Mode - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Programming Models
5. DLL in reset starts new locking event. Wait for the DLL to lock to
the new frequency. Note DLL locking time depending on the
to
DDR2_CLK
• 1:2 – 3000
• 1:3 – 7500
• 1:4 – 10000
6. Assign the required external DDR2 banks in the
7. Wait 8 core cycles for effect latency.
8. Program the refresh rate control register (
9. Program the timing parameters in the
10.Program all MR and EMR3-1 settings in the
11.Enable DDR size (row, column, bank) in the
12.Start the power-up sequence with the
external bank calibration.
The device now ready for any access.

Frequency Change in Precharge Power-Down Mode

This command allows programs to change the DDR2 clock during run
time. Two different usage cases are relevant: changing the VCO or chang-
ing the core to DDR2 clock. Power-down requires careful software
control since the DRAM is not refreshed. The clock frequency change
must happen in a specific time window (typically t
x t ). If you change the VCO frequency the
REFI
equation must be met. If it cannnot be met (most cases) the entire clock
3-130
www.BDTIC.com/ADI
ratio is:
cycles
CCLK
cycles
CCLK
cycles
CCLK
ADSP-214xx SHARC Processor Hardware Reference
register.
EPCTL
).
DDR2RRC
register.
DDR2CTL1
DDR2CTL5-3
register.
DDR2CTL0
bit. Wait for DLL
DDR2PSS
max = 8 x t
RAS
× 4096 < 9 × t
CLKIN
CCLK
registers.
or 9
REFI
REFI