Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 613

For more information on core clock setting, see
Management Registers" on page A-6
Power Management Registers" on page
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
PCG Effect Latency
After the PCG registers are configured the effect latency is shown below.
The latency to start the
source as described below.
Input clock through
• If divisor value is 0 or 1 (bypassed) the latency is 1
• For other divisor values the latency is 3
Input clock through
• If divisor is 0 or 1 (bypassed) the latency can vary from 0 to 1 oscil-
lator period. This is because clock generation starts with the
immediate positive edge of the
• For other divisor values the latency can vary between 2 to 3 oscilla-
tor periods. This is because clock generation starts with the third
positive edge of
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
and
A-12.
depends on the divisor value and input
CLKOUT
PCLK
CLKIN
CLKIN
.
CLKIN
Precision Clock Generator
"ADSP-2146x Power
"ADSP-2147x/ADSP-2148x
PCLK
cycles
PCLK
.
cycle
14-19