Synchronization Of Pwm Groups - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Operation Modes
in each half period (or 2 x
mode, improved accuracy is possible since different values of the duty
cycles registers are used to define the on times in both the first and second
halves of the PWM period. As a result, it is possible to adjust the on-time
over the whole period in increments of
effective PWM accuracy of
200 MHz clock). The achievable PWM switching frequency at a given
PWM accuracy is tabulated in
Table 7-4. PWM Accuracy in Single- and Double Update Modes
Resolution (bits)
8
9
10
11
12
13
14

Synchronization of PWM Groups

The register enables or disables the four PWM groups in any
PWMGCTL
combination. This provides synchronization across the four PWM groups.
The
PWM_SYNC_ENx
without enabling the outputs through
asserted, the 4 PWM outputs are automatically synced to the initially pro-
grammed period. In most cases, all
enabling the
PWM_ENx
chronizes the four groups.
7-24
www.BDTIC.com/ADI
for the full period). In double update
PCLK
in double update mode (or 10 ns for a
PCLK
Table
Single Update Mode PWM
Frequency (kHz)
× 8
200 MHz ÷ 2 2 = 390.63
195.3
97.7
48.8
24.4
12.2
6.1
bits in this register can be used to start the counter
bits of the four PWM groups at the same time syn-
ADSP-214xx SHARC Processor Hardware Reference
. This corresponds to an
PCLK
7-4. In Table 7-4,
Double Update Mode PWM Frequency
(kHz)
8
200 MHz ÷ 2
390.6
195.3
97.7
48.8
24.4
12.2
. So when
PWM_EN
bits can be initialized to zero,
SYNC
= 200 MHz.
PCLK
= 781.25
is
PWM_ENx