Tcb Storage - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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Table 2-13. FFT Input Chain Pointer Register (CPIFFT)

Bit 19 of the chain pointer register is the program controlled interrupt

) bit. This bit controls whether an interrupt is latched after every

DMA in the chain (when set = 1), or whether the interrupt is latched after

the entire DMA sequence completes (if cleared = 0). If a program contains

a single chained DMA then the PCI interrupt is generated coincident with

the start of next TCB loading.

However, if running multiple DMA channels this coincidence is no longer

true since there are different DMA channel priorities versus interrupt

Also, interrupt requests enabled by the

TCB Storage

This section lists all the different TCB memory allocations used for DMA

chaining on the peripherals. Note that all TCBs must be located in inter-

nal memory except SPORTs, where TCBs can exist in external memory.

ADSP-214xx SHARC Processor Hardware Reference

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bit only effects DMA channels that have chaining enabled.

I/O Processor

Next chain pointer address

Program controlled interrupt

0 = no interrupt after current TCB

1 = interrupt after current TCB

Coefficient select for next TCB

0 = next TCB is data TCB

1 = next TCB is coeff TCB

bit are maskable with

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