Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 673

TIMERx_I
PERIOD
P_BUF
COUNTER
IRQ
Figure 16-8. EXT_CLK Timing
Interrupts
This section describes all relevant registers and hardware to raise and ser-
vice interrupts.
Table 16-5 provides an overview of timer interrupts.
Table 16-5. Timer Interrupt Overview
Interrupt Source
GP Timer (PWM,
Width Capture, Ext
Watchdog, 2 chan-
nels)
Sources
Each timer generates a unique interrupt request signal. A common register
latches these interrupts so that a program can determine the interrupt
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
cycle
cycle
P P - 1
Interrupt Interrupt
Condition Completion
– Timer expire
– Timer overflow
Peripheral Timers
P
P - 2 2 1
Interrupt Acknowledge Default
W1C (Write 1-to-clear)
TMxSTAT + RTI
instruction
P
0 P P - 1 P - 2
sync delay
IVT
P2I, P10I
16-17