Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 577

Receive Status Register (DIRSTAT). The receiver also detects errors in
the S/PDIF stream. These error bits are stored in the status register, which
can be read by the core. Optionally, an interrupt may be generated to
notify the core on error conditions.
Receive Channel Status Registers (DIRCHANAx/Bx). These registers
provide status information for receiver subframe A and B.
Clocking
The fundamental timing clock of the S/PDIF is peripheral clock/4
( /4).
PCLK
S/PDIF Transmitter
The following sections provide information on the S/PDIF transmitter.
Functional Description
The S/PDIF transmitter, shown in
and it's inputs and outputs can be routed via the SRU. It receives audio
data in serial format, encloses the specified user status information, and
converts it into the biphase encoded signal. The serial data input to the
transmitter can be formatted as left-justified, I
word widths of 16, 18, 20 or 24 bits.
block.
The serial data, clock, and frame sync inputs to the S/PDIF transmitter
are routed through the signal routing unit (SRU).
see "DAI Signal Routing Unit Registers" on page A-118.
The S/PDIF transmitter output may be routed to an output pin via the
SRU and then routed to another S/PDIF receiver or to components for
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Sony/Philips Digital Interface
Figure 13-1 resides within the DAI,
2
S, or right-justified with
Figure 13-2 shows detail of the AESs
For more information,
13-7