Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 669

registers are read-only in WDTH_CAP mode. The period and pulse width
measurements are with respect to a clock frequency of
Figure 16-5 shows a flow diagram for WDTH_CAP mode. In this mode,
the timer resets words of the count in the
0x0000 0001 and does not start counting until it detects the leading edge
on the
TIMERx_I
TIMERx_PERIOD
TIMERx_I
Figure 16-5. Timer Flow Diagram – WDTH_CAP Mode
When the timer detects a first leading edge, it starts incrementing. When
it detects the trailing edge of a waveform, the timer captures the current
value of the count register (=
width registers. At the next leading edge, the timer transfers the current
value of the count register (=
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
signal.
CORE BUS
PCLK
TIMERx_COUNTER
PULSE
LEADING
EDGE
DETECT
TIMER_ENABLE
TMxOVF
PERIOD_CNT
INTERRUPT
LOGIC
INTERRUPT
TMxCNT
TMxCNT
Peripheral Timers
PCLK
register value to
TMxCNT
TIMERx_WIDTH
RESET
PULSE TIMERx_I
TRAILING
EDGE
DETECT
÷ 2) and transfers it into the
÷ 2) into the
TMxPRD
÷ 2.
TMxW
period register.
16-13