Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 728

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registers) and enabling DMA using the

can be interrupted by resetting the

DMA request that is already in the pipeline completes normally.

DMA Chaining

DMA chaining is enabled by setting the

receive control registers. When chaining is enabled at the end of a current

DMA, the next set of DMA parameters are loaded from internal memory

and a new DMA starts. The index of the memory location is written in the

chain pointer register. DMA parameter values reside in consecutive mem-

ory locations as shown in

the chain pointer register contains address 0x00000 for the next parameter

The following sections provide information on the UART and interrupt

If UART core interrupts (core RX INT of UART ) are routed via

the DPI interrupt, programs do not need to read the

also clears the

www.BDTIC.com/ADI

Table 2-16 on page

provides an overview of UART interrupts.

ADSP-214xx SHARC Processor Hardware Reference

bit in the control register. A

bit in the transmit and

2-15. Chaining ends when

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