Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 368

IIR Accelerator
5. Configure the index, modifier, and length entries in the TCBs to
point to the corresponding channel's data buffer, coefficient buffer
and output data buffer.
The location of the first channel's TCB is written to the chain
pointer register in the accelerator.
6. Program the global control register
a. The accelerator starts and loads the first channel's TCB,
loads coefficients and Dk values of all the 6 biquads into
local storage, then loads the TCB of the second channel,
and finally loads coefficients and Dk values of all the 8
biquads.
b. Once all the coefficients and Dk values are loaded, the con-
troller loads the TCB of first channel and fetches the input
sample. It then starts calculating the first biquad of the first
channel.
c. The accelerator calculates the output of the first biquad and
then updates the intermediate results for that biquad. Then
it moves to the next biquad of that channel and repeats the
biquad processing until all the biquads for that channel are
done and the final result is stored to memory.
d. The accelerator repeats this process with next sample until
one window of the corresponding channel is processed.
Once the window is done, the accelerator saves the index
values to memory and moves to the next channel. After both
channels are done, the accelerator waits for core
intervention.
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ADSP-214xx SHARC Processor Hardware Reference
bit for 2 channels.
FIR_NCH