Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 749

The TWI controller's special-case start and stop conditions include:
• TWI controller addressed as a slave-receiver
If the master asserts a stop condition during the data phase of a
transfer, the TWI controller concludes the transfer (
• TWI controller addressed as a slave-transmitter
If the master asserts a stop condition during the data phase of a
transfer, the TWI controller concludes the transfer (
indicates a slave transfer error (
• TWI controller as a master-transmitter or master-receiver
If the stop bit is set during an active master transfer, the TWI con-
troller issues a stop condition as soon as possible to avoid any error
conditions (as if data transfer count had been reached).
Slave Mode Addressing
With the appropriate selection of 7-bit addressing using the
the corresponding number of address bits (
the address phase of a transfer.
Master Mode Addressing
Whether enabled as a master-transmitter or master-receiver with 7-bit
addressing using the
and data transfers as required. This includes generating the repeated start
condition, re-transmission of the 7-bits of the first address byte, and
acknowledgement and generation of a new transfer direction change (indi-
cated by the
TWIMLEN
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Two Wire Interface Controller
TWISERR
bit, the TWI master performs all addressing
TWIMLEN
bit).
TWISCOMP
TWISCOMP
).
TWISLEN
) are referenced during
SADDR
).
) and
bit,
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