Interrupts - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Interrupts

Table 3-27. External Read Index Calculation Delay Line DMA
Equation
EIEP + TL[N]
EIEP + TL[N] + 1 × RMEP
EIEP + TL[N] + 2 × RMEP
...
EIEP + TL[N] + RCEP × RMEP
EIEP + TL[N + 1]
EIEP + TL[N + 1] + 1 × RMEP
Interrupts
There are two external port DMA channels. The following sections
describe the two ways of triggering interrupts.
overview of external port interrupts.
Table 3-28. External Port Interrupt Overview
Interrupt Source Interrupt Condition
External port DMA RX/TX complete –internal transfer
DMA (2 chan-
nels)
3-114
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Result
First read address for tap N
Second read address for tap N
Third read address for tap N
Last read address for tap N
First read address for tap N + 1
Second read address for tap N + 1
Interrupt
Completion
completion
–access completion
ADSP-214xx SHARC Processor Hardware Reference
Table 3-28 provides an
Interrupt Default IVT
Acknowledge
RTI instruction P9I, P13I