Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 200

DDR2 DRAM Controller (ADSP-2146x)
7. Issue a load MR command. Wait t
ter (200 cycle counter)—any read command is issued only after
this counter expires.
8. Issue a precharge all command. Wait t
9. Issue two or more auto refresh commands, with a t
between each command. Wait t
10.Issue a load MR command with low to A8 (bit 8), to initialize
operating parameters without resetting the DDR2 DLL. Wait for
t period.
MRD
11.Issue a load EMR command.
12.Wait for t
13.Wait for the 200 cycle counter to expire before performing any
read operation.
14.Start the calibration of the DLL within the processor's DDR2
controller.
The DDR2 is now ready for normal operation.
Initialization Time
After setting the power-up start bit, the controller starts internal and
external calibration routines which are described below. The actual cycles
may vary due to different timing specifications.
• Best case (one external DDR2 bank assigned). The entire power up
requires 680 DDR2 initialization + 660 external bank calibration =
around 1340 DDR2 cycles.
• Worst case (all external DDR2 banks assigned). Entire power up
requires 680 DDR2 initialization + (4 x 660 external bank calibra-
tion) = around 3320 DDR2 cycles.
3-70
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period.
MRD
ADSP-214xx SHARC Processor Hardware Reference
period. Also trigger a coun-
MRD
period.
RPA
period.
RFC
period in
RFC