Clocking Ami/Ddr2 - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Clocking AMI/DDR2


The SDRAM clock ratio settings are independent from the periph-
eral clock (
Table 3-2. External Port Clock Frequencies
CCLK:SDCLK
Clock Ratio
1:2.0
1:2.5
1:3.0
1:3.5
1:4.0

To obtain certain higher SDRAM frequencies, the core frequency
may need to be reduced.
Clocking AMI/DDR2
The fundamental timing clock of the external port is DDR2 clock
( ). The AMI/DDR2 controller is capable of running up to core
DDR2_CLK
clock/2 speed (
CCLK
the programmed DDR2 clock (
information processor instruction rates, see the appropriate processor data
sheet.

The DDR2 clock ratio settings are independent from the periph-
eral clock (
3-6
www.BDTIC.com/ADI
).
PCLK
CCLK = 400 CCLK = 333
MHz MHz
N/A 166
160 133
133 111
114 95
100 83
/2) and can run at various frequencies, depending on
DDR2_CLK
).
PCLK
ADSP-214xx SHARC Processor Hardware Reference
CCLK = 266
MHz
133
106
88
76
66
) to core clock (
CCLK
CCLK = 200
MHz
100
80
67
57
25
) ratios. For