Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 138

Functional Description
EP CORE BUS
SPEP (SPORT) BUS
PERIPHERAL
CORE BUS
EP IOP
REGISTER
IOD1 (EP)
DMA BUS
DMA
32 ARBITER
Figure 3-1. External Port Functional Block Diagram (SDRAM)
Figure 3-2 shows a diagram of the external port for the ADSP-2146x pro-
cessor (containing a DDR2 interface).
As shown in the figures, the external port is a fundamental block since
every access in the external memory space is handled by this port. The
AMI or the SDRAM/DDR2 controller modules act as peripherals to the
external world and as such they are responsible for filling the buffers with
data based on the protocol used. The external port also keeps track of the
two DMA channels which can serve as data streams via the external and
internal memory.
3-8
www.BDTIC.com/ADI
64
32
DMA
0
DMA
1
ADSP-214xx SHARC Processor Hardware Reference
AMI
ARBITER
AMI
CONTROLLER
SDRAM
SDRAM
CONTROLLER
ARBITER
RD
WR
ACK
ADDR
DATA/MSx
RAS
CAS
WE
CKE
CLK
SDA10, DQM