Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 799

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SPI Boot Packing

In all SPI boot modes, the data word size in the shift register is hardwired

to 32 bits. Therefore, for 8- or 16-bit devices, data words are packed into

the shift register to generate 32-bit words least significant bit (LSB) first,

which are then shifted into internal memory. The relationship between

the 32-bit words received into the

need to be placed in internal memory is shown in the following sections.

For more information about 32- and 48-bit internal memory addressing,

see the "Memory" chapter in the SHARC Processor Programming Reference.

) before a DMA transfer to internal memory occurs for 16-bit

SPI devices. For 8-bit SPI devices, four words shift into the 32-bit receive

shift register before a DMA transfer to internal memory occurs.

Figure 23-5. Instruction Packing for Different Hosts

When booting, the processors expect to receive words into the

ter seamlessly. This means that bits are received continuously without

For more information, see "Core Transfers" on page 15-20.

different SPI host sizes, the processor expects to receive instructions and

data packed in a least significant word (LSW) format.

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

23-5, two words shift into the 32-bit receive shift reg-

[0x8C000] 0x1122 33445566

[0x8C001] 0x7788 AABBCCDD

System Design

INSTRUCTIONS IN

INTERNAL MEMORY

Chapters

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