Interrupts - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

IIR Accelerator
Accelerator input and output channels are used to connect to internal
memory.

Note that the
to program individual IIR channels having different control
attributes.

Interrupts

The IIR accelerator has two interrupts that are programmable through the
registers (
PICR
source bits are used to connect IIR interrupts to the peripheral
ACC1I
interrupt inputs of the core.
Table 6-4. Overview of IIR Interrupts
Interrupt Source
IIR (2 channels)
One interrupt line is shared by all the DMA interrupts and the other by
MAC status interrupts. Separate status registers are provided to further
differentiate the various sources.
Interrupt Sources
There are two interrupt sources associated with the accelerator. The
bit in the
IIR_CCINTR
the bit generates window complete interrupt and when cleared (default),
an interrupt is generated after all the channels are complete.
Window Complete Interrupt – This interrupt is generated at the end of
each channel when all the output samples are calculated corresponding to
a window and updated index values are written back.
6-64
www.BDTIC.com/ADI
register is part of the IIR TCB. This allows
IIRCTL2
Appendix B, Peripheral Interrupt
Interrupt Condition Interrupt
Completion
- Window Complete - Internal trans-
- Channel Complete fer completion
- MAC status
register controls these interrupts. When set,
IIRCTL1
ADSP-214xx SHARC Processor Hardware Reference
Control). The
ACC0I
Interrupt Default IVT
Acknowledge
RTI instruction Need to route
ACCxI (PICRx)
to any PxxI
and