Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 643

2. The
SPIEN
system.
3. The
MME
4. An SPI interrupt is generated.
These four conditions persist until the
1-to-clear (W1C-type) software operation. Until the
SPI cannot be re-enabled, even as a slave. Hardware prevents the program
from setting either
When is cleared, the interrupt is deactivated. Before attempting to
MME
re-enable the SPI as a master, the state of the
be checked to ensure that it is high; otherwise, once
set, another mode-fault error condition will immediately occur. The state
of the input pin is reflected in the input slave select status bit (bit 7) in the
register.
SPIFLG
As a result of
SPIEN
drivers ( ,
MOSI MISO
output pins revert to control by the processor flag I/O module registers.
This may cause contention on the slave-select lines if these lines are still
being driven by the processor.
Debug Features
The following sections provide information on features that help in
debugging SPI software.
Shadow Receive Buffers
A pair of read-only (RO) shadow registers for the receive data buffers,
and
RXSPI RXSPIB
ters,
RXSPI_SHADOW
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
control bit in
SPICTL
status bit in
SPISTAT
or
SPIEN SPIMS
and being cleared, the SPI data and clock pin
SPIMS
, and ) are disabled. However, the slave-select
SPICLK
are available for use in debugging software. These regis-
and
RXSPIB_SHADOW
Serial Peripheral Interface Ports
is cleared, disabling the SPI
is set.
bit is cleared by a write
MME
MME
while is set.
MME
SPI_DS_I
SPIEN
, are located at different addresses
bit is cleared, the
input pin should
and are
SPIMS
15-27