Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 941

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Table A-72. WDTSTATUS Register Bit Descriptions (RO)

Current Count (WDTCURCNT)

timer. Reads to

safety, this register can only be updated when WDT configuration space is

unlocked by programming the command in the

cannot be stored directly in

Enabling the watchdog timer does not automatically reload

ory-mapped register that must be accessed with 32-bit reads and writes.

Trip Counter (WDTTRIP)

The WDT contains a software programmable register

the number of times that the WDT can expire before the

continually asserted until the next time hardware reset is applied. This reg-

ister is unaffected by WDT generated reset. This register can only be

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Watchdog Expired. Indicates that DSP core attempted to write

to WDT configuration space without an unlock "command". Bit

is set when the above exception occurs. Software can determine

whether the watchdog has expired by interrogating this bit. This

is a sticky bit that is set whenever the watchdog timer count

Watchdog Error. Indicates that watchdog timer has expired. Bit

is set when counter expires. Attempts by the core to write to the

WDT configuration space without an unlock command, causes

the WDT to expire and this condition is captured in the watch-

dog exception field. This is a sticky bit that is set whenever the

above exception occurs.

return the current count value. For added

Registers Reference

, but are instead copied from

Chapters

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