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The delay (in number of
ter time-outs must be written to the
triggers an auto-refresh command to the external SDRAM bank. Programs
should write the
power-up sequence is triggered. Change this value only when the SDC is
idle as indicated in the
To calculate the value to write to the
equation.
RDIV
Where:
• f
=
SDCLK
• t
= SDRAM refresh period
REF
• NRA = Number of row addresses in SDRAM (refresh cycles to
refresh whole SDRAM)
• t
= Active to precharge time (
RAS
ory control register) in number of clock cycles
• t
= RAS to precharge time (in the SDRAM memory control reg-
RP
ister) in number of clock cycles
This equation calculates the number of clock cycles between required
refreshes and subtracts the required delay between bank activate com-
mands to the same bank (t
that in the case where a refresh time-out occurs while an SDRAM cycle is
active, the SDRAM refresh rate specification is guaranteed to be met. The
result from the equation is always rounded down to an integer. Below is
an example of the calculation of
with a 133 MHz SDRAM clock.
• f
= 133 MHz
SDCLK
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
cycles) between consecutive refresh coun-
SDCLK
value to the
RDIV
SDRRC
register.
SDSTAT
×
f
t
SDCLK
REF
≤
----------------------------------- -
NRA
frequency (SDRAM clock frequency)
SDCLK
= t
RC
RAS
RDIV
field. A refresh counter time-out
RDIV
register before the SDRAM
register, use the following
SDRRC
(
)
–
t
+
t
RAS
RP
bits in the SDRAM mem-
SDTRAS
+ t
). The t
value is subtracted, so
RP
RC
for a typical SDRAM in a system
External Port
3-33
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