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Error Interrupts
The
bit (bit 2 of the
UARTLSIE
tion on an independent interrupt channel when any of the following
conditions are raised by the respective bit in the UART line status register
(
):
UARTLSR
• Receive overrun error (
• Receive parity error (
• Receive framing error (
• Break interrupt (
In core transfers, the receive interrupt is generated for the following cases.
• When
UARTRBR
• On a receive overrun error
• On a receive parity error
• On a receive framing error
• On a break interrupt (
• When
UARTTHR
• An address detect (
• A transmit complete (
The ISRs can evaluate the status bit field within the UART interrupt iden-
tification register (
more than one source is signalling, the status field displays the one with
the highest priority. Interrupts also must be assigned and unmasked by the
processor's interrupt controller. The ISRs must clear the interrupt latches
explicitly.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
UARTIER
)
UARTOE
)
UARTPE
)
UARTFE
)
UARTBI
is full
held low)
RXSIN
is empty
) interrupt (for 9-bit mode)
UARTADI
UARTTXFI
) to determine the signalling interrupt source. If
UARTIIR
UART Port Controller
register) enables interrupt genera-
) interrupt
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