Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 902

Peripheral Registers
Table A-42. FFTCTL1 Register Bit Descriptions (RW) (Cont'd)
Bits
6
31–7
Control Register (FFTCTL2)
The FFT control register, shown in
Table A-43, is used to set up individual FFT parameters (such as length)
and how the module process the FFT, such as data packing.
31 30
NOVER256 (28–21)
15
FFT_LOG2HDIM (15–12)
VDIM (11–7)
FFT_LOG2VDIM (6–3)
Figure A-34. FFTCTL2 Register
A-76
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Name Description
FFT_DBG Debug Mode Enable.
0 = Disable
1 = Enable
Reserved
29 28 27 26 25 24
14 13 12 11 10 9 8
ADSP-214xx SHARC Processor Hardware Reference
Figure A-34 and described in
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1 0
HDIM (20–16)
FFT_RPT
Accelerator Repeat
FFT_CPACKIN
Complex Word Input Packing
(<512 words)
FFT_CPACKOUT
Complex Word Output Packing
(<512 words)