Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 185

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Each subsequent data-out appears on the

signal in a source synchronous manner.

The RL is equal to an additive latency (AL) plus CAS latency (CL). The

CL is defined by the mode register (MR), similar to the existing SDRAM.

The AL is defined by the

CAS Latency (CL) = 3

Additive Latence (AL) = 2

READ latency = RL - AL + CL - 5

DQSQ = NOMINAL

Figure 3-12. Burst Read

The burst write command, shown in

the rising edge of the clock. The address inputs determine the starting col-

umn address. Write latency (WL) is defined by a read latency (RL) minus

one and is equal to (AL + CL – 1) and is the number of clocks of delay

that are required from the time the write command is registered to the

clock edge associated to the first

A data strobe signal (

nally a 1/2 clock prior to the WL. The first data bit of the burst cycle must

be applied to the

lowing the preamble.

ADSP-214xx SHARC Processor Hardware Reference

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pins low while holding

) should be driven low (preamble) nomi-

pins at the first rising edge of

pin in phase with the

3-13, is initiated by having

External Port

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