Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 557

Clocking
The fundamental timing clock of the ASRC module is peripheral clock/4
( /4) and is operating in slave mode only.
PCLK
Functional Description
Figure 12-1 shows a top level block diagram of the SRC module and
Figure 12-2 shows architecture details. The sample rate converter's FIFO
block adjusts the left and right input samples and stores them for the FIR
filter's convolution cycle. The
address to the FIFO block and the ramp input to the digital-servo loop.
The ROM stores the coefficients for the FIR filter convolution and per-
forms a high-order interpolation between the stored coefficients. The
sample rate ratio block measures the sample rate by dynamically altering
the ROM coefficients and scaling the FIR filter length and input data.
The digital-servo loop automatically tracks the
sample rates and provides the RAM and ROM start addresses
SRCx_FS_OP
for the start of the FIR filter convolution.

Unlike other peripherals, the sample rate converters own local
memories (RAM and ROM) which are dedicated for the purpose of
sample rate conversion only.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Asynchronous Sample Rate Converter
counter provides the write
SRCx_FS_IP
and
SRCx_FS_IP
12-5