Internal Sdram Bank Access; Single Bank Access - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

SDRAM Controller (ADSP-2147x/ADSP-2148x)
• t = 64 ms
REF
• NRA = 8192 row addresses
• t = 6
RAS
• t = 3
RP
RDIV
This means
RDIV
ister is written with 0x406.
The value must be programmed to a nonzero value if the SDRAM
RDIV
controller is enabled. When
is not supported and can produce undesirable behavior. Values for
can range from 0x001 to 0xFFF.

Notice that some SDRAM vendors use separate timing specifica-
tions for the row active time (t
The controller does ignore the t
the equation t
cations must meet (especially for extended temperature range) the
modification of t
without performance degradation (t

Internal SDRAM Bank Access

The following sections describe the different scenarios for SDRAM bank
access.

Single Bank Access

The SDC keeps only one page open at a time if all subsequent accesses are
to the same row or another row in the same bank.
3-34
www.BDTIC.com/ADI
6

× ( ) × ×
133 10 64

-------------------------------------------------------------------
=
 8192
is 0x406 (hex) and the SDRAM refresh rate control reg-
= 0, operation of the SDRAM controller
RDIV
= t + t
RC RAS RP
specification resolves the timing equation
RAS
ADSP-214xx SHARC Processor Hardware Reference
3 –

( )
10
( )

6 3
1030
– + =

) and row refresh time (t
RC
spec. For auto-refresh, it use
RFC
. However since both timing specifi-
= t + t
RFC RAS
RDIV
).
RFC
).
RP