Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 512

Effect Latency
SPORT Loopback
When the SPORT loopback bit,
the serial port is configured in an internal loopback connection as follows:
SPORT0/SPORT1 work as a pair, SPORT2/SPORT3 work as a pair,
SPORT4/SPORT5 work as a pair and SPORT6/SPORT7 work as a pair.

The
SPL
The loopback mode enables programs to test the serial ports internally and
to debug applications. In loopback mode, either of the two paired
SPORTS can be transmitters or receivers. One SPORT in the loopback
pair must be configured as a transmitter; the other must be configured as a
receiver. For example, SPORT0 can be a transmitter and SPORT1 can be
a receiver for internal loopback. Or, SPORT0 can be a receiver and
SPORT1 can be the transmitter when setting up internal loopback.
LoopBack Routing
The SPORTs support an internal loopback mode by using the SRU.
more information, see "Loop Back Routing" on page 9-40.
Buffer Hang Disable (BHD)
To support debugging buffer transfers, the processors have a buffer hang
disable ( ) bit. When set (= 1), this bit prevents the processor core from
BHD
detecting a buffer-related stall condition, permitting debugging of this
type of stall condition.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
10-54
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SPL
bit applies to all non multichannel modes.
ADSP-214xx SHARC Processor Hardware Reference
(bit 12), is set in the register,
SPMCTLx
For