Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 560

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Functional Description

rate, a fast mode has been added to the filter. When the digital-servo loop

starts up or the sample rate is changed, the digital-servo loop kicks into

fast mode to adjust and settle on the new sample rate. Upon sensing the

digital-servo loop settling down to some reasonable value, the digital-servo

loop kicks into normal or slow mode. During fast mode, the

SRCx_MUTE_OUT

SRC which avoids clicks and pops.

The FIR filter is a 64-tap filter in the case of

loading in the starting address of the RAM address pointer and the ROM

address pointer from the digital-servo loop at the start of the

period. The FIR filter then steps through the RAM by decrementing its

address by 1 for each tap, and the ROM pointer increments its address by

convolution is complete. The convolution is performed for both the left

and right channels, and the multiply/accumulate circuit used for the con-

volution is shared between the channels.

ically alter the coefficients in the ROM for the case when

, the sample rate ratio is updated if it is different by more than

comparison. This is done to provide some hysteresis to prevent the filter

length from oscillating and causing distortion.

However, the hysteresis of the (

cause phase mismatching between two SRCs operating with the same

input and output clocks. Since the hysteresis requires a difference of more

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bit of the SRC is asserted to remind the user to mute the

) × 64 taps for the case when

. The FIR filter performs its convolution by

. Once the ROM address rolls over, the

) sample rate ratio circuit is used to dynam-

. The ratio is calculated by comparing the out-

counter to the output of an

, the ratio is held at one. If

periods from the previous

periods to update the

ADSP-214xx SHARC Processor Hardware Reference

) ratio circuit can

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