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MTMDMA0ACT (WO)
Memory Write DMA Status
MTMFLUSH (WOC)
1=Flush the FIFO and reset the
read/write pointers
Figure A-30. MTMCTL Register (RW)
Pulse Width Modulation Registers
The following registers control the operation of pulse width modulation
on the processor.
Global Control Register (PWMGCTL)
This register enables or disables the four PWM groups, in any combina-
tion and provides synchronization across the groups. Note that disable bits
have higher priority over the enable bits (bit 1 higher as bit 0 and so on).
This 16-bit register is shown in
For the PWM global control register, the traditional read-modify-write
operations to disable the PWM group have changed. The action is to
directly write—this simplifies the enable/disable of the PWM groups and
can be done with fewer instructions. For example, instead of the following
code:
ustat3 = dm(PWMGCTL);
bit set ustat3 PWM_DIS0;
dm(PWMGCTL) = ustat3;
Use:
ustat3 = PWM_DIS0;
dm(PWMGCTL) = ustat3;
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
31 30
29 28 27 26 25 24
15
14
13
12
11 10
9
8
Figure
/* PWM General Control Register */
/* disables group 0 */
Registers Reference
23 22
21 20 19 18 17 16
7
6
5
4
3
2
1
0
A-31.
MTMDMA1ACT
Memory Read DMA Status
MTMDEN
MTM DMA Enable
0=Disable
1=Enable
A-67
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