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The delay (in number of
refresh counter time-outs must be written to the
counter time-out triggers an auto-refresh command to the external DDR2
bank. Write the
power-up sequence is triggered. Change this value only when the DDR2
controller is idle.
To calculate the value that should be written to the
the following equation:
= (
RDIV
DDR2_CLKx
• DDR2 Clock = DDR2 system clock frequency
• t
= DDR2 maximum average auto refresh period (in us). (Note
REFI
t
= t
REFI
• t
= Active to precharge time (
RAS
ister) in number of clock cycles
• t
= RAS to precharge time (in the
RP
of clock cycles
This equation calculates the number of clock cycles between the required
distributed refreshes, and subtracts the required delay between bank acti-
vate commands to the same bank (t
subtracted, so that in the case where a refresh time-out occurs while a
DDR2 cycle is active, the refresh rate specification is guaranteed to be
met. The result from the equation should always be rounded down to an
integer.
Below is an example of the calculation of
ory in a system with a 200 MHz clock.
= 200 MHz
DDR2_CLKx
= 7.8 μs
t
REFI
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
DDR2_CLKx
value to the
RDIV
DDR2RRC
×
t
) – (t
REFI
RAS
/Number of row addresses)
REF
cycles) desired between consecutive
field. A refresh
RDIV
register before the DDR2
DDR2RRC
+ t
) where:
RP
bit in the
DDR2_RAS
register) in number
DDR2CTL1
= t
+ t
). The t
RC
RAS
RP
for a typical DDR2 mem-
RDIV
External Port
register, use
reg-
DDR2CTL1
value is
RC
3-67
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