Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 906

Peripheral Registers
31 30
15
FIR_RND (16–14)
Rounding Mode
FIR_TC
Two's-Complement Format
FIR_FXD
Fixed-point Accelerator Select
FIR_CCINTR
Channel Complete Interrupt
Figure A-35. FIRCTL1 Register
Table A-47. FIRCTL1 Register Bit Descriptions (RW)
Bits
0
5–1
7–6
8
9
10
A-80
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29 28 27 26 25 24
14 13 12 11 10 9 8
Name Description
FIR_EN FIR Enable.
0 = FIR disabled
1 = FIR enabled
FIR_CH32–1 Number of Channels. Programmable between 0–31
0 = FIR_CH1
31 = FIR_CH32
Reserved
FIR_DMAEN DMA Enable.
0 = DMA disabled
1 = DMA enabled
FIR_CAI Channel Auto Iterate.
0 = Processing stops once all channels are over
1 = Moves to first channel and continues processing in a
loop when all channels are over
Reserved
ADSP-214xx SHARC Processor Hardware Reference
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1 0
FIR_RND (16–14)
Rounding Mode Select
For Floating-point Mode
FIR_EN
Accelerator Enable
FIR_CH (5–1)
Number of Channels
FIR_DMAEN
DMA Enable
FIR_CAI
Channel Auto Iterate