External Instruction Fetch - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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frequency change requires self-refresh mode. The DDR2 DDR2 input

core to DDR2 clock ratio change can be made under following condition:

1. The ODT must be turned off.

2. Put the DDR2 DDR2 in precharge power down mode (

pin goes low). A minimum of 2 DDR2 clock cycles must occur

after the clock frequency change.

3. The core to DDR2 clock divider is allowed to change only within

the minimum and maximum operating frequency specified for the

particular speed grade. During input clock frequency change,

4. Once the input clock frequency has changed, stable new clocks

must be provided to DRAM before the precharge power down may

5. Reset the on-chip DLL and wait until it locks to new frequency.

6. Depending on new the clock frequency, an additional MRS or

EMRS command may needed to appropriately set the writes, laten-

cies and other parameters. During the DLL re-lock period, ODT

must remain off.

7. Before writing to

mode register happens during

External Instruction Fetch

The section describes the software programming steps needed for the suc-

cessful operation of external instruction fetch through the external port.

Note only the additional steps for code execution are illustrated. For tim-

ing related settings refer to

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

must be held at stable low levels.

pin goes high). This ensures the DLL reset via

"Functional Description" on page

External Port

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