Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 877

AMI Status Register (AMISTAT)
This 32-bit register provides status information for the AMI interface and
can be read at any time. This register is shown in
described in Table
15 14 13
AMIS
External Interface Status
Figure A-22. AMISTAT Register
Table A-27. AMISTAT Register Bit Descriptions (RO)
Bit Name
0 AMIMS
1 AMIS
15–2 Reserved
SDRAM Registers
This section provides complete descriptions of the SDRAM controller's
memory-mapped registers for SDRAM programming.
Control Register (SDCTL)
The SDRAM memory control register includes all programmable parame-
ters associated with the SDRAM access timing and configuration. This
32-bit register is shown in
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
A-27.
12 11 10 9 8 7 6 5
Description
AMI External Bus Master.
0 = SDRAM Controller controls the external bus
1 = AMI controls the external bus (default)
For ADSP-2146x processors bit 0 is always (=1) since the DDR2
and AMI are not shared
External Interface Status.
0 = AMI interface idle
1 = AMI access pending
Figure A-23
Registers Reference
Figure A-22
4 3 2 1 0
AMIMS
External Bus Master
and described in
and
Table A-28.
A-51