Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 954

DAI Signal Routing Unit Registers
Table A-76. Group B Sources – Serial Data (Cont'd)
Selection Code
101100(0x2C)
101101(0x2D)
101110(0x2E)
101111(0x2F)
110000(0x30)
110001(0x31)–111101(0x3D)
111110 (0x3E)
111111 (0x3F)
Frame Sync Routing Control Registers
(SRU_FSx, Group C)
The frame sync routing control registers (see
Figure A-69) route a frame sync or a word clock to the serial ports, the
SRC, the S/PDIF, and the IDP. Each frame sync input is connected to a
frame sync source based on the 5-bit values described in the group C
frame sync sources, (listed in

SPORTs 6 and 7 receive their frame syncs from other routed
sources but cannot route their own frame syncs to other SPORTs
or other peripherals internally through SRU. If externally needed,
they have to be routed through the DAI pins.
A-128
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Source Signal
SPORT6_DA_O
SPORT6_DB_O
SPORT7_DA_O
SPORT7_DB_O
DIT_O
Reserved
LOW
HIGH
Table A-77).
ADSP-214xx SHARC Processor Hardware Reference
Description (Source Selection)
SPORT 6A Data
SPORT 6B Data
SPORT 7A Data
SPORT 7B Data
SPDIF TX BiphaseStream
Logic Level Low (0)
Logic Level High (1)
Figure A-65 through