Fft Accelerator Tcb - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

TCB Storage

FFT Accelerator TCB

The FFT accelerator supports circular buffer chained DMA.
and Table 2-21
Table 2-20. FFT Input TCBs
Address
CP[18:0]
CP[18:0] + 0x1
CP[18:0] + 0x2
CP[18:0] + 0x3
CP[18:0] + 0x4
CP[18:0] + 0x5

The input TCB controls both data and coefficients. Bit 20
(
COEFFSEL
whether the TCB is for loading data or coefficients. For coefficient
TCBs (
COEFFSEL
( ) and base length (
ILFFT
Table 2-21. FFT Output TCBs
Address
CP[18:0]
CP[18:0] + 0x1
CP[18:0] + 0x2
CP[18:0] + 0x3
CP[18:0] + 0x4
CP[18:0] + 0x5
2-18
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shows the required TCBs for chained DMA.
Register
CPIFFT
IBFFT
ILFFT
ICFFT
IMFFT
IIFFT
) of the input chain pointer register (
=1), circular buffering and the input length
IBFFT
Register
CPOFFT
OBFFT
OLFFT
OCFFT
OMFFT
OIFFT
ADSP-214xx SHARC Processor Hardware Reference
CPIFFT
) TCB fields are ignored.
Table 2-20
), indicates